An important process during the fabrication of semiconductor devices is formation of metal interconnects that provide electrical paths between conductive layers. Metal interconnects consist of trenches that provide horizontal connections between conductive features and vias or contacts that provide vertical connections between metal layers. Metal layers are insulated from each other by a dielectric layer to prevent capacitance coupling or crosstalk between the metal wiring. Recent improvements in interlevel dielectric layer (ILD) performance have involved replacing SiO2 that has a dielectric constant (k) of about 4 with a low k material that has a k value between 2.5 and 3.5 such as carbon doped SiO2 and fluorine doped SiO2 which is also called fluorosilicate glass (FSG).
One form of carbon doped oxide is called SiCOH and is typically deposited by a chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD) method from an organosilane precursor and oxygen source to afford a Si content of 15-18 atomic %, an oxygen content of 28-30 at. %, a carbon content of 16-18 at. %, and a hydrogen content of 36-38 atomic %. SiCOH includes Si—O, Si—C, and Si—H bonds according to infrared analysis. Other low k dielectric materials that are used as ILD layers include polymers such as hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), poly(arylether), and fluorinated polyimide which are applied by a spin-on procedure and have good cap filling capability. HSQ and MSQ (CH3SiO1.5) typically do not reach a low k value until heated to temperatures of about 400° C. These low k dielectric materials are normally cured by baking from about 350° C. to 450° C. in order to drive out residual water, solvents, or traces of monomers that could outgas in subsequent thermal cycles and degrade device performance. For example, water may have a corrosive effect on copper and traces of nitrogen containing compounds can poison a photoresist patterning step used to form vias or trenches in the dielectric layer.
A transmission delay in the wiring which is commonly known as an RC delay is a function of capacitance between the metal layers and resistance within the wiring. RC delay is not only improved by switching to a low k dielectric material that reduces parasitic capacitance but also by replacing aluminum with copper wiring that has a lower resistivity.
Low k dielectric layers, especially carbon doped silicon oxide, HSQ, and MSQ exhibit a high porosity and low density which yields a soft film that has stress related issues. For instance, a chemical mechanical polish (CMP) step is typically used to planarize low k dielectric layers or a metal layer adjacent to a low k dielectric material. The etching and polishing action during a CMP step is likely to scratch or form an indentation in the surface of a soft insulating material. These surface defects will degrade device performance if not corrected by an expensive rework process.
Although a carbon doped oxide layer and SiCOH in particular is becoming more popular as ground rules shrink in newer semiconductor devices, the material must be densified in a post-deposition step or water is easily absorbed during a storage period that may vary from a few minutes to several hours before the next step in the fabrication scheme. Water uptake leads to a large increase in dielectric constant which defeats the purpose of the low k dielectric material.
Prior art methods for densifying low k dielectric layers include a plasma treatment with N2 and He in U.S. Pat. No. 6,465,372. The densification is preferably done with N2 at a temperature of about 400° C. and prevents loss of carbon during subsequent oxidizing processes such as plasma etches. The densification leaves the C—H and Si—C bonds intact and does not change the refractive index or dielectric constant of the film.
U.S. Pat. No. 6,403,464 provides a method for removing moisture from a low k dielectric layer and is a high density nitrogen plasma treatment at a temperature of from 350° C. to 450° C. U.S. Pat. No. 6,436,808 employs a NH3/N2 plasma treatment of an ILD layer such as SiCOH that is repeated one or more times during a damascene process. This method maintains Si—H bonds that are needed for a constant low k value.
A popular means of producing an interconnect structure is by a damascene technique in which an opening 14 such as a via shown in FIG. 1 is etched in a stack comprised of dielectric layer 13 on an etch stop layer 12 that has been deposited on a substrate 10. Substrate 10 is comprised of at least one conductive layer 11 and one or more dielectric layers (not shown). The opening is initially formed in a photoresist layer (not shown) that serves as an etch mask for the pattern transfer.
In FIG. 2, a diffusion barrier layer 15 is deposited in the opening 14 by a CVD method followed by deposition of a metal layer 16 to fill the opening. Diffusion barrier layer 15 protects metal layer 16 from traces of water or other chemicals contained in dielectric layer 13 or in etch stop layer 12. A CMP step is then used to lower the metal layer 16 to be coplanar with dielectric layer 13.
One problem associated with the damascene process is that a soft dielectric layer 13 is susceptible to the formation of defects such as a divot 17 and a scratch 18. For example, a SiCOH layer that is not densified is likely to suffer divot and scratch defects 17, 18 that may be removed by a rework process but such an effort adds considerable expense to the fabrication scheme. An uneven surface surrounding the metal layer 16 is not tolerable. One concern is that a subsequent photoresist patterning step on dielectric layer 13 will have a small process window because of an uneven thickness resulting from divots 17. Therefore, a method that hardens dielectric layer 13 prior to a polish step is necessary. Furthermore, dielectric layer 13 is preferably transformed into a more thermally stable layer in order to avoid a breakdown during subsequent thermal cycles.
One stabilization approach mentioned in U.S. Pat. No. 6,028,015 treats a low k dielectric layer with H2 plasma. The process is believed to convert a dangling bond on Si to a Si—H bond and also prevents moisture from being attracted to the reactive Si sites. Similarly, a fluorine doped SiO2 layer is treated with hydrogen plasma in U.S. Pat. No. 6,103,601. In U.S. Pat. No. 6,372,301, a hydrogen plasma treatment of a fluorinated SiO2 layer improves adhesion to a subsequently deposited diffusion barrier layer in a via. Another post-deposition treatment of a low k dielectric film involves a densification of a Si—O—C layer in NH3 at 400° C. or optionally with a He, Ar, or N2 plasma. A hydrogen ion implant to inhibit cracking in a low k film is performed with a plasma immersion ion implantation in U.S. Pat. No. 6,346,488.
A plasma treatment with Ar/H2 is described in U.S. Pat. No. 6,204,204 for reducing resistivity in a TaN barrier layer. Another plasma treatment in U.S. Pat. No. 6,528,423 improves resistance in a SiC barrier layer to Cu migration.
A post-deposition method is also desirable that is able to further improve the insulating property of a low k dielectric layer. Prior art methods can prevent a dielectric constant from becoming larger by blocking water absorption but these processes do not teach how to lower a k value of a deposited film. Unfortunately, none of the prior art methods are capable of densifying a low k dielectric layer, improving its thermal stability and reducing its dielectric constant in a single process.